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Memory hierarchy
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#	Item
71	Sequoia: Programming the Memory Hierarchy Kayvon Fatahalian Timothy J. Knight Mike Houston Mattan Erez Daniel Reiter Horn Add to Reading List Source URL: theory.stanford.edu Language: English - Date: 2006-07-31 12:45:40 Computer cluster Cell Distributed memory Burroughs MCP Task parallelism Multi-core processor Computing Parallel computing Computer architecture
72	The Cache Performance of Blocked Monica S. Lam, Add to Reading List Source URL: www-suif.stanford.edu Language: English - Date: 2003-10-16 22:29:20 Computer hardware Compiler optimizations CPU cache Central processing unit Data Memory hierarchy Cache-oblivious algorithm Loop tiling Cache Computer memory Computing
73	Reinventing Scheduling for Multicore Systems Silas Boyd-Wickizer, Robert Morris, M. Frans Kaashoek (MIT) A BSTRACT cache in other cores, but if the application stays on one Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2015-04-29 10:31:17 Microprocessors Central processing unit Computer memory Parallel computing CPU cache Multi-core processor Scheduling Thread Memory hierarchy Computing Computer hardware Computer architecture
74	Petascale Software Challenges William Gropp www.cs.illinois.edu/~wgropp Petascale Software Challenges •  Add to Reading List Source URL: gladiator.ncsa.illinois.edu Language: English - Date: 2011-05-26 14:47:21 Petascale Supercomputers Parallel computing Scalability Memory hierarchy Parallel programming model Computing Concurrent computing Programming paradigms
75	PetascaleSoftware-new.pptx Add to Reading List Source URL: gladiator.ncsa.illinois.edu Language: English - Date: 2010-05-20 14:16:48 CPU cache Sizeof Petascale Memory hierarchy Sparse matrix Parallel computing Transmission Control Protocol Computing Computer memory Computer hardware
76	Microsoft PowerPoint - Exa-Yotta-yotta-yotta.ppt Add to Reading List Source URL: www.pdsi-scidac.org Language: English - Date: 2008-12-03 18:04:51 File system Disk storage Memory hierarchy Information science Information Computer storage media Computer hardware Solid-state drive
77	Design and Evaluation of a Compiler Algorithm for Prefetching Todd C. Mowry, Monica S. Lam and Anoop Gupta Computer Systems Laboratory Stanford University, CA 94305 Add to Reading List Source URL: www-suif.stanford.edu Language: English - Date: 2006-06-25 21:11:32 Computer hardware Computer programming CPU cache Loop nest optimization Cache Memory hierarchy Software pipelining Lookup table Acumem SlowSpotter Computing Computer memory Compiler optimizations
78	Taming the Power Hungry Data Center Extraordinary power savings are achieved by integrating the world’s highest performance storage. ©2007 Fusion-io, All Rights Reserved. Add to Reading List Source URL: www.fusionio.com Language: English - Date: 2012-07-06 14:33:51 Computer peripherals Server hardware Solid-state drive Computer storage Central processing unit Hard disk drive Fusion-io IOdrive Memory hierarchy Computer hardware Computing Computer memory
79	Staged Reads : Mitigating the Impact of DRAM Writes on DRAM Reads ∗ Niladrish Chatterjee University of Utah Naveen Muralimanohar Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2012-01-10 00:00:20 Dynamic random-access memory CPU cache Random-access memory Write buffer Memory controller CAS latency Memory hierarchy DDR3 SDRAM RLDRAM Computer memory Computer hardware Computing
80	Sandbox Prefetching: Safe Run-Time Evaluation of Aggressive Prefetchers Seth H Pugsley1 , Zeshan Chishti2 , Chris Wilkerson2 , Peng-fei Chuang3 , Robert L Scott3 , Aamer Jaleel4 , Shih-Lien Lu2 , Kingsum Chow3 , and Raje Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2014-01-10 15:51:59 Computer architecture Prefetcher CPU cache AMD 10h Memory hierarchy Cache NForce Lookup table Acumem SlowSpotter Computer hardware Computing Computer memory

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